Three-phase transistorized oscillator power supply



Aprll 6, 1965 R. o. BARBER ETAL THREE-PHASE TRANSISTORIZED OSCILLATORPOWER SUPPLY Filed oct. v, 1960 5 sheets-sheet 1 RMN A TTORNEY April 6,1965 m. BARBER Em 3,117,420

THREE-PHASE TRANSISTORIZED OSCILLATOR POWER SUPPLY INVENTORS A TTOR/VE Y5 Sheets-Sheet 3 April 6, 1965 R. o. BARBER ETAL THREE-PHASETRANSISTORIZED OSCILLATOR POWER SUPPLY Filed oct. 7, 1960 4 TTOR/VE'Y afR M ARM. RR WW/m j n t N M M@ A m M n j i m if a m m N, VL Y Rel 1T RRRRR F I m/m .V wJ y \M Ry Rw ww y UN 4*] B .QM .w Q SN n RNN/ f n .SSRJRR. .Q P J R R R n Nw @n MR/R Nm. sus

April 5, 1955 R. o. BARBER L11-,en 3,177,420

THREE-PHASE TRANSISTORIZED OSCILLATOR POWER SUPPLY I April 6 1965 R. o.BARBER ETAL 3,177,420

THREE-PHASE TRANSISTORIZED OSCILLATOR POWER SUPPLY Filed Oct. 7, 1960 5Sheets-Sheet 5 A rra/#Nev if/ME United States Patent O 3,177,420TEE-PHASE TRANSISTRIZED GSCILLA'I'GR NEWER SUPPLY This invention relatesto a static inverter power supply system for providing preciselydisplaced three-phase Ialternating current power from a direct currentpower supply. Specifically it relates to a static inverter system forproviding 400 cycle three-phase alternating current power from a 25 to30 volt direct current source which has primary utility in aircraftinstallations but which can be used in any other similar installationWhere there is a need for such equipment. Inverters for producing singlephase alternating current power from a direct current source are notuncommon but difiiculties arise when precisely displaced three-phasepower is required from the direct current power source and it is theobject of the present invention to provide such an inverter system.

In the present instance a Ahigh frequency oscillator powered by a directcurrent source is used .as the basic power source, the output of whichis divided down through a series of binary dividers or counters to asuitable frequency which is then applied to a ternary divider to providethe desired output frequency and thence through logic gate circuits to athree-phase output where accurate and precise spacing is maintained atall times between the three phases.

The objects and advantages of this invention will be better-understoodfrom the following description with reference to the figures of theaccompanying drawings in which:

FIGURE 1 is a block diagram illustrating the components of the completeinverter system;

FIG. 2 is a block diagram illustrating the components of the basicoscillator, frequency division section and logic gate section forsupplying three-phase power;

FIG. 3 is a diagram illustrating the manner in which FIGS. and 6 fittogether;

FIG. 4 is a series of graphs illustrating the wave shapes of the voltageobtained at various indicated locations;

FIG. 5 is a portion of the detailed circuit diagram of lthe oscillator,binary counter, divider and logic section of our inverter;

FIG. 6 is the remainder of that detailed circuit diagram of our inverterwhich should be considered together With FIG. 5 as shown in FIG. 3;

FIG. 7 is a block diagram illustrating the clock and gate controls fordeveloping the precisely spaced threephase output; and,

FIG. 8 is a graph showing the relative timed clock and gate conditionsto develop the precisely phased threephase output.

Referring first to FIG. 1 there is shown therein a high frequencyoscillator 2 which serves as the main source of high frequency current.This is, of course, supplied with direct current power from the powersupply 24 in order to drive the same and is in this case a crystalcontrolled oscillator which operates at a very accurate frequencyoutput. The output of the oscillator is fed into a section which may betermined a frequency division or splitting section for dividing down thefrequency of the power and which terminates in a gate logic circuitproviding a three-phase output. This is shown in FIG. l as a blockidentified as logic circuit 4 but actually it includes much more than apure logic circuit as will be clear from the following detaileddescription.

ICC

The output of the logic circuit block 4 is actually three-phase powerand each phase is connected individually through a pre-amplifier, poweramplifier, magnetic amplifier and filter of its own to a final outputwinding. This is illustrated in FIG. l by three separate channelsidentified as A, B and C. For example, the channel identified as A has apre-amplifier 6 which is connected to the -output of the first phasefrom the logic circuit 4 and which is in turn connected to a poweramplifier S, thence through a magnetic amplier 10 and a filter 12 to anoutput winding 14. Inductively associated with the output winding 14 ina Y connection in a feedback winding 16 which is connected to a feedbackamplifier I8 and thence into the magnetic amplifier to control theamount of amplification. Each of the other phases are exactly the sameas the first but lamplify and control the voltage flowing through itsphase at electrical degree displacement from the others The output ofthese three together are applied to the output windings 14, 20 and 22 todrive whatever equipment it is desired with alternating current power.The power supply indicated at 24 is shown connected into the logiccircuit but it actually provides power for the whole system.

Referring now more particularly to FIG. 2 which specifically illustrateshow the high frequency of the oscillator is divided or broken down intoa suitable lower output frequency, the block units of FIG. 2 from theoscillator 2 on are all elements included in block 4 identitled as thelogic circuit in FIG. l. In this instance the oscillator has beendesigned to operate at a fixed frequency of 76.8 kc. in order to providea final output frequency of 400 cycles. As mentioned the oscillator iscrystal controlled so that it maintains a very accurate frequency. Theoutput of the oscillator is applied first to an amplier section 26 wherethe 76.8 kc. signal is amplified. The signal is then squared by section28 to square up the sinusoidal wave and applied to binary I or firstfrequency dividing circuit 30 which divides the frequency in half. Theoutput of this binary I circuit has, therefore, a frequency of 38.4 kc.In succession the signal is then sent through a series of dividingcircuits binary II-32, binary III-34, binary IV-36, binary V-38 andlastly binary VI-fttl. Through this succession of frequency divisionsthe frequency is changed from 38.4 kc. to 19.2 kc., 9600 cycles, 4800cycles, 2400 cycles and lastly 1200 cycles, respectively, as labeled onthe blocks. It is obvious that from the output of the last binary VI-40means must be provided to reduce the frequency from 1200 to 400 cyclesand at the same time provide a three-phase output precisely spaced at120 electrical degrees. This is accomplished in two steps, first througha ternary division section 42 which reduces the frequency to 400 cyclesand thence through a gate logic circuit 44 which properly switches theoutput to threephase output lines atthe correct time. The final outputof this chain is, therefore, a precisely spaced three-phase 400 cycleoutput. These would be the signals applied to the different channels A,B and C as indicated in FIG. l.

FIG. 3 is merely included to show how FIGS. 5 and 6 should be laidtogether in order to form a complete circuit diagram.

Referring now more particularly to FIG. 4 there are shown in that figuregraphs of the shape of the various voltage wave forms found at differentpoints indicated numerically in the general circuit, FIG l. The voltagewave form as shown in the first graph 46 of FIG. 4 appears at the outputof the oscillator circuit 2 at point indicated as ll. It is to be notedthat this is not a complete sinusoidal wave voltage but that thepositive half waves have been clipped to form more of a square waveaire/iso indicating that the wave has passed through the square wavesection 28. At point 2A there is obtained a 40G cycle square wavevoltage as shown at 48 and it is indicated by being labeled 2A at theleft in FIG. 4. This voltage is indicated as going positive at timezero, reverse at 180 electrical degrees to negative, reverse again topositive at 360 electrical degrees, etc. The 400 cyclevoltages'appearing at 2B and 2C are shown in the next two succeedinggraphs Sti and 52 which are likewise labeled 2B and 2C to indicate wherethey appear. At time Zero the voltage at 2B is indicated as beingnegative but it goes positive -at 120 degrees, thus lagging phase A bythat amount, remains there for additional 180 degrees, then backpositive again showing a phase displacement to the iirst phase shown at2A of 120 degrees. In like manner the curve 52 showing the shape of thevoltage applied to the C channel and spcciiically to point 2C is shownto be on positive at time Zero, to go negative at 60 degrees and toremain there for 180 degrees, reversing to positive to again indicatethe proper 120 degrees spacing of the three phases A, B and C at points2A, 2B and 2C, respectively.

The following graphs in FlG. 4 indicate the further changes in the waveform as the voltage progresses only through the A channel since the sameresults would obtain in each yor the other two channels and thediscussion would be repetitive. Therefore, following the voltage wavesthrough channel A alone, when the wave reaches the point 3A we find thatthe amplitude oi the wave indicated at 5d has increased since it haspassed through the pre-ai ipliiier 6 but that its shape and phase is thesaine as it was in wave form iii and it is only the aniplitude that hasvaried. Output voltage wave form Sli, labeled preamplifier output, isthen applied to the po fver amplifier 3 and the resultant wave shown at56, indicated as appearing at point dA, is, as would he expected, anadditional amplitude increase. The effect of magnetic amplifier Il@ andthe resultant wave form appearing at point 5A, FlG. 1, is indicated at58, FlG. 4, and in this case it is seen that this is a stabilizedregulated wave whose amplitude is controlled to give only a desiredoutput, the feedback preventing the output from exceeding a certainvalue. in order now to return the square wave appearing at the output ofthe magnetic amplier to the sinusoidal form in which it is desired touse the same, the square wave torni 5S appearing at point 5A is appliedto the input of the filter l2 which smooths it out and, therefore, atpoint 6A there is obtained a substantially sinusoidal output Wave 6dwhich appears on the output winding ld for use in desired apparatus. Thesame anipliiication, squaring and smoothing occurs in each one of theother channels B and C as each applies its output in desired phasedrelation to output coils 2@ and 22, respectively, obtaining preciselyspaced three-phase power at 40G cycles from the loutput windings iid,2li and Referring now more particularly to the detail circuit of thestatic inverter shown in FlGS. 5 and 6, the power oscillator 2 consistsof two transistors 62 and 6d which are controlled by a quartz crystal doconnected in feedback relation between the collector electrode 68 or output of transistor ddand the base electrode 7@ or input of transistor 62.These two transistors are properly biased by being supplied with powerfrom power line '72 whose terminal at the eXtreme right of HG. 6 isconnected to a source of power of l2 volts as indicated. This power line'72 is connected through resistances 74 and 76 to the collectorelectrodes '7d and o@ of the transistors 62 and 6d, respectively. Theemitter electrodes titl and 82 of the transistors 62 and 6d areconnected through biasing resistors 8d and 8d to ground line 83 whoserighthand terminal in FlG. 6 is marked ground A resistance 9d isconnected between the base electrode 7n of transistor o2 and ground anda further biasing resistor 92 is connected between the collectorelectrode 7d and base electrode 7d. The resistances 7d, 92 and i B'provide a voltage divider for supplying the proper bias voltages to thetransistor 62.' 'llic collectorV electrode 73 of the transistor 62 isconnected through a condenser 9d to the base electrode 9d or" thetransistor 'ed and a biasing resistor 98 is connected between thecollector electrode d@ and the base electrode 9o of this transistor.This is a two stage oscillator, the rst stage d2 acting as the mainoscillator and the second stage od functioning as an amplifier and phaseinverter so that the feedback signal through the crystal is in theproper phase. This Voscillator suppliesV power at a frequency of 76.8kc. and has a sine Wave output which is applied to the input or baseelectrode intl or the transistor m2 in the next stage through couplingresistance l? shunted by condenser @9. y

rEhe transistor to2 acts as both an amplier and as a wave squaring stageand is. connected directly across between the power line 72 and theground line Sil, its collector electrode find being connected to thepower line through biasing resistance ldd and its emitter electrode itltbeing directly connected to ground line 8.

The sine wave output of the oscillator 2 applied to the irst stageincluding transistor liiZ is amplified and since this stage is designedto be turned on and oir rapidly it also squares the signal to produce anamplified square wave signal.

it is next desired to reduce the frequency of the signal and this squarewave output from transistor lh?. is applied to line il@ connecteddirectly to the collector electrode ldd or transistor 1h32 and to theinput of the iirst binary counting circuit indicated previously asbinary l consisting of two transistors M2 and lid. These binary circuitsare used only for frequency division and are conventional binary oriiip-ilop circuits, one half of the circuit conducting on each cycle tocut the frequency output in hah, Power is supplied to this binarycircuit from power supply line 72 through resistors il@ and lid.Resistor iid is connected to collector 2li@ ot transistor i12 and itsemitter is directly connected to ground line 2S. ln a symmetrical mannercollector t28 of transistor iii/i is connected to resistor M8 andemitter Zilli of transistor lid is connected to ground line liti. it isdesired to maintain the base electrodes otthese two transistors at aslight positive bias and as illustrative line 2% is in this caseindicated as being connected to a source of power of +3 volts. Baseelectrode of transistor M2 is connected to line 2do through resistor 2inand base electrode 23.2 of transistor Md is similarly connected to line2% through resistor 2id. Base electrode 2% of transistor M2 iscross-connected to collector l28 of transistor ille through resistor 2idwhich is shunted by condenser 2id. Symmetrically, base electrode 222 oftransistor 1M is cross-connected to collector 2h@ of transistor M2through a resistor 22h shunted by condenser 222.

The input line liti to this binary stage is commonly connected totwokcontrol diodes 22d and 226. Diode 2.2/1.1 is also connected througha resistor 22S to one end of resistor 2id and through a condenser 23d tooase 2% of transistor i112. Symmetrically, diode 226 is connectedthrough resistor 232A to one end of resistor 22@ and through a condenser23d Vto base 2il2 of Vtransistor ld. A power supply line 236 ispermanently connected to a -6 volt source and this line and its tie line238 connected thereto are directly connected to a pair oi diodes 24d and242 in the binary l circuit. The diode 2d@ is also connected to thecollector electrode .Ci-titi of transistor lf2 and diode 242 isconnected to collector 128 of transistor lid. These diodes are calledclamping diodes and prevent the spccitic collector electrode to whicheach is connected from going below -6 volts under any condition.V Itmight be mentioned here that lines 236 and 23S are connected throughdiodes to all of the collectors of all of the stages of the inverterrorn the amplifier and ywave squaiing section on.

Binary I operates as a flip-flop circuit, that is one side conductswhile the other is olf and each negative going signal causing aswitching from the non-conducting to the conducting state and viceversa. Assuming that transistor 114 is conducting and that transistor112 is cut off, the application of a negative pulse to line 110 causes acharging of gate condenser 218 which drives the base 20S negative toturn on transistor 112. Turning transistor 112 on makes the base 212 oftransistor 114 positive which turns it olf. The next negative pulseagain causes the base 212 to go negative to turn `transistor 114 on and112 o so that with every alternate negative pulse transistor 114conducts which provides a one-half frequency output.

A similar binary or ip-liop circuit including transistors 120 and 122,previously identified as binary II, follows next in order but will notbe described in detail as its circuitry is the same as binary I. Thesetransistors 120 and 122 are supplied from the power line throughresistances 124 and 126 and the signal output from the first binarycounting circuit is supplied to binary II from the collector electrode128 of transistor 114 through line 130 and thence alternately throughrectiiiers 132 and 134 and their associated gate circuits to the basecircuits of the transistors 120 and 122. This pair of tnansistors againdivides the frequency in two and applies the output to line 136 whichcouples into the next binary group, binary III, including transistors138 and 140. The output of binary III is coupled through line 142 tobinary IV including transistors 144 and 146 for further frequencydivision and that output again applied to coupling line 148 into binaryV including transistors 156 and 152. Through these iive binary countersor frequency dividers the frequency has been reduced from 76.8 kc. to2400 cycles. This, however, is not quite low enough so it is necessaryto utilize one last stage of frequency division which is provided bybinary VI coupled to binary V through line 154. Binary VI includestransistors 156 and 158 and on the collector electrodes of transistors156 and 158 a frequency of 1200 cycles is now obtained and appliedthrough line 160 to the input of the ternary division or three halvesdivision.

The purpose of the remainder of the circuitry shown in FIGS. 5 and 6 isto reduce the frequency of .the power to 400 cycles and to divide itinto three-phase power. In order to accomplish this two additionalbinary circuits identified as D and E are provided together with seventransistor gates identified as F, G, H, I, L, M and N. These all combineto develop on line 244 electrical voltage for a first phase A as wasindicated in FIG. 1, on line 246 power for phase B which is preciselyspaced at 120 degrees and on line 248 power for phase C. Line 160 iscommonly coupled to the input of the two binary circuits indicated as Dand E, since it is connected directly to a pair of rectiiiers 162 and164 in the binary circuit D yand also to two input rectiers 166 and 163in the input circuit of the binary E. In this binary portion of thecircuit it is desired to develop signals to control the transistor gateswitching means F, G, H, I, L, M and N to give a 400 cycle output on thethree properly phased and timed transmission lines 244, 246 and 24S. Theoutput of binary VI, 1200 cycles, triggers both binary D and E andtogether therewith provides conductive signals in proper phased relationto control switching means for the desired three-phase output as willnow be described. Binary circuits D and E are not exactly like binarycircuits I-IV, nor are they like each other. They are all substantiallyalike but are designed to require more factors to be present beforeswitching occurs. The differences are the addition in binary D of acontrol signal diode 250 connected through condenser 252 to base 254 oftransistor R and two control signal diodes 253 and 255 connected inparallel and through condenser 256 to the base 25S of transistor R. In asimilar manner in binary E control diode 260 is connected-throughcondenser 262 to base electrode 264 of transistor S and a control diode266 is connected through condenser 268 to base 270 of transistor S'.Conductor 272 interconnects diode 250 of binary D with diode 266 ofbinary E. A tie line 274 connected to conductor 272 is connected to thecollector electrode of transistor R and then extends on to the input oftransistor H. Diode 253 is connected through tie line 276 to conductor278. Conductor 273 extends from the collector of transistor R to theinput circuits of transistors G, J and L. The last diode 255 in binary Dis connected to line 230 which extends from the collector of transistorS to the inputs of transistors J and M. Control diode 260 of binary E isconnected through line 232 to the collector of transistor S and to theinput of transistor F.

It is desired to have each of the binaries D and E operate at a 400cycle repetitive rate but as will be evident from the following detaileddescription it will not be a balanced wave. These two outputs, togetherwith the control of the last regular binary VI, control the seven gatecircuits in a manner to be described to provide the three-phase output.

In order to obtain a 400 cycle pulse in the D and E binary circuits,control switching must be built in as described. Logic equations canalso be written which enable a clearer understanding of the operation.It has been worked out that if the following conditions are present thebinary circuits D and E will produce a 400 cycle repetitive signal froma 1200 cycle input. The operating logic equations are; let R be turnedon when R is on, S is on, and the master pulse from the last binary suchas binary VI is applied, which can be called K. To indicate this, apoint adjacent the collector of transistor 158 is labeled K and asimilar location adjacent the collector of transistor 156 labeled K. Theequation can then be written for binary D;

On the other hand R' is turned off at any :time that itis on and themaster pulse is applied or R'=Rr (2) Equations can also be written forthe E binary which states that S is turned on any time that R is onandthe master pulse is applied or that S is turned off at any time thatit is on and the master pulse is applied. It is to be further pointedout that only negative going pulses actuate the binaries.

Referring now to FIG 8 there is illustrated therein how the two binariesD and E produce the 400 cycle unbalanced waves from the 1200 cycleoutput of binary VI with .the described logic controls by the controldiodes to provide the equation logic. The first graph 390 at the top ofFIG. 8 illustrates the voltage at point K. This is a 1200 cycle wavevoltage since this is a point in binary VI. The second curve 302 is theinverse of that voltage appearing at opposite point K' since when oneside is on or conducting the other is oif. At time zero it is assumedthat both R sand S are off and when K falls or goes negative at Zero allfactors of Equation 1 are met and R is turned on as shown at 554 in thethird graph 306. At 60 K. goes positive but this does not cause anychange since only negative pulses cause switching and R stays on.However, at i. again goes negative. This time Equation 2 applies and R'is turned oif. At this same instant, however, the same master pulse isapplied to S. S has been ofi since it could not turn on with the firstnegative pulse at zero time since R was oif. At 120, however,momentarily R is on after the negative pulse is applied before it turnsoli and this permits S to switch on as shown on curve 308. S will remainon until the next negative going pulse of K at 240 and will turn off atthat peint as shown in graph 308, FIG. 8. However, R

cannot turn back on at this point as oneof the'requisites of Equation 1was that S be off before it could turn on and it, therefore, remains olffor next negative going pulse to repeat. This provides unbalanced pulsesat R' and S' repeating at a 400 cycle rate. Curves of the other half ofeach binary R and S are, of course, the inverso of R yand S' and areshown at 307 and V309 on FIG. 8.

Having now developed the various timed pulses which are produced at thevarious binary outputs shown at locations K, K', R', R, S and S it isnow desired to describe how these pulses control the seven gates toapply the proper output voltages on lines 244, 246 and 248 for a fullthree-phase output. standing, this portion of the circuit diagram hasbeen diagrammatically re-drawn and is shown in FlG. 7 and the transistorgates are indicated therein by the letters which previously defined thetransistors in the circuit of FIGS. 5 and 6.

Referring now specifically to FIG. 7, there is shown therein thethree-phase output lines 244, 2426 and 24S which are also labeled phaseA, phase B and phase C. From FlG. 6 it is seen that phase A. iscontrolled primarily by transistor L since it is directly connected tothe collector 301i thereof. Transistor L is in turn controlled by eitherone of two signals, one from the binary terminal R through control diode303 and the other from the output of transistor F through diode 305. Ifeither one of these inputs goes negative, transistor L will conduct andallow voltage to appear from the -12 volt power supply on the line. Thisis diagrammatically shown in FIG. 7 by the two lines extending from therectangular-shaped representation L to the left. The first line 278connects the transistor L directly with the output of transistor R andas this point goes negative will cause the same to conduct. Thetransistor L is also connected through line 320 to the output oftransistor F.

Transistor F on the other hand is also controlled by two signalvoltages. One of these is the voltage appearing at binary terminal S'and is applied through diode 307.

The connection is shown on FIG. 7 as line 322. The

other control signal for gate transistor F is the voltage appearing atthe 1200 cycle master pulse binary K' and is applied through diode 309.The connecting line is shown on both FIGS. 5 and 7 at 324. Therefore,When either of these points K and S go negative, gate transistor L willbe driven into conduction and the pattern of the wave form so generatedwill later be specifically described.

In like manner the wave form appearing on output line 246, phase B iscontrolled primarily by gate transistor M. Transistor M in turn iscontrolled through diode 311 by the pulse appearing at location Sthrough line 280. Transistor M is also controlled by a second gatetransistor G which is gated by the pulses appearing at R and K throughdiodes 313 and 315, respectively. These signals are applied throughlines 278 and 326.

Lastly, the voltage Wave appearing on line 248 for phase C is primarilycontrolled by gate transistor N which in turn is controlled by a pair ofgate transistors H and I through diodes 317 and 319. H is in turncontrolled by the pulses appearing at R' and K' through diodes 321 and323 and Vtheir associated lines 274 and ln order to assist in theunderdegree cycle is divided into siX different portions of 604 each,marked across the top of the Whole diagram in FlG. 8 with zero time atthe left and these portions will, therefore, be referred to hereafter bytheir associated numbers. It is noted on FIG. 7 that transistor F iscontrolled by the voltage at K' and the voltage at S'. Beginning at timezero and considering only K', K' from curve 302 is noted as beingnegative at time periods 2, 4 and 6.

326, respectively. Transistor l, on the other hand is controlled by thepulses appearing at peints S and R applied through diodes 325 and 2127and lines 260 and 278, respectively. As before Vmentioned, Whenever anegative going signal appears at any one of the control points R, R', S,S' or K or K' then any particular gate connected thereto is opened andthe opening of one portion of a gate is suiicient to allow conductionfor the system controlled thereby.

Referring now to the lower group of curves shown in FIG. 8, anexplanation will follow as to how, through these described pulses andgates the desired signal shape Therefore, transistor F would be onduring these periods due to this pulse. This is indicated to curve 330by the long dash line in these sections labeled at the righthand sideK'. During this cycle S from curve 308 is also negative during periods 1and 2 and 5 and 6. This is indicated on curve F by the short dash linesin these squares just below the main curve labeled S at the right. It isnow evident that transistor F will be on at all times except during timeperiod 3 which is from 120 to 180 electrical degrees and during thatperiod it will be olf. This is shown in curve 330.

So far, therefore, transistor L connected thereto and controlled by Fand the current on line 244 would be on for only 60 electrical degreesout of the whole cycle. lt is, therefore, necessary to further opentransistor L for an additional adjacent the lirst sixty to form auniform On cycle. This is accomplished by trigger ing transistor L alsothrough R. Referring back to curve 307 it is noted thatv in the curvefor point R this point goes negative at time zero and stays negative for120 which is indicated by the dash and dot lines under curve 332 fortransistor L. Also transistor F is turned on for time period 3 as beforedescribed and indicated by the dash line so there is now obtained an Onperiod of 180 from zero to 180 and an Off period of 180 from 180 to 360.This provides the voltage on phase A and is a 400 cycle voltage, a thirdof the original 1200.

ln like manner curve 334 is developed to illustrate the On and Offeriods of transistor G which assists in the control of the voltagedeveloped for phase B. In this instance, from FIG. 7 it is noted thattransistor G is controlled by pulses from R andK. Referring to the curve302 We again note that K' is negative in time periods 2, 4 and 6. Thisis indicated by the long dash lines across these time periods for curve334 indicated by K at the right of the curve. turned on by this pulseduring these periods. It is also controlled by R and referring to curve307 We note that R is negative during time periods 1 and 2 and this isindicated by the short dash lines extending across these time periods.This pulse tends to turn on transistor G during time periods l and 2.The fact that it has already been turned on by the pulse from the pointK during time period 2 makes no difference. As a result of these twocontrol pulses transistor G is turned on during time periods 1, 2, 4 and6 and offV during periods 3 and 5. Referring back again to FIG. 7, sincetransistor G controls nal gate transistor M for phase B an additional Ycontrol pulse must be obtained to lill in the gap in time period 4. Thisis obtained from point S. Specifically referring now to curve 336identified also as M and again remembering that transistor M will beconductive only when negative pulses are applied thereto, it is foundthat M will have negative pulses applied thereto during time periods 3and 5 from transistor G .as shown in curve 334 and as identitied incurve 336 by the long dash lines,

This transistor will, therefore, beV

and it will also have applied thereto negative control pulses directlyfrom point S and by referring to the curve representing the voltages atthat location we see from curve 309 that those voltages go negativeduring time periods 3 and 4 which is indicated by the short dash lines.Therefore, while there is some overlap we now find that the transistor Mwill be nonconductive during time periods l and 2, conduct through timeperiods 3, 4 and 5, and be non-conductive during time period 6. Thisagain gives us our desired wave form of 180 degrees on and 180 degreesoff and it is to be further noted that it is spaced 120 electricaldegrees from phase A.

In similar manner the voltage appearing on phase C will now be developedand it is here noted that two control gate transistors are used tocontrol the final transistor. There will be developed, therefore, acurve for both gate transistors H and I. The curve for transistor H isshown at 338 and by reference back to FIG. 7 it is noted that transistorH is controlled by the pulses appearing on R and K. By reference tocurve 306 it is noted that R is negative during time periods 3, 4, 5 and6. This is indicated just under curve 338 by the long dash linesidentified as R at the right. This transistor is also controlled by thepulses appearing at K and by reference to curve 302 it is noted that Kis negative during time periods 2, 4 and 6. This is indicated by theshort dash lines appearing across those time periods and identified as Kat the righthand side. The step curve 338, therefore, indicates an OEperiod for time period 1 and an On period for the other five periods ofthe cycle. The last curve to be developed is curve 340 which relates tothe operation of gate transistor J. Gate transistor I is shown in FIG. 7as controlled by the pulses appearing at points S and R. By reference tocurve 307 representing R it is found that this is negative during timeperiods 1 and 2 which would turn on transistor I and this is indicatedfor curve 340 by the long dash lines under the main curve and identifiedby R on the righthand side. Reference to curve 309 indieating thecondition at the S point shows that S is negative during time periods 3and 4 and this is indicated by the short dash lines during those timeperiods and the let-ter S at the right. When these two transistors H andI combine to control transistor N it will be noted that there is anegative pulse available during time period 1 due to transistor H asshown by the long dash line and H in the righthand side and also during5 and 6 due to transistor J as shown by the short dash lines and I onthe righthand side to cause the transistor N to conduct and the rest ofthe time it is off. This produces the third phase for phase C which isagain spaced 120 electrical degrees from the other two.

The result of these timed and gated circuits is, therefore, athree-phase precisely spaced current on the three output lines 244, 246and 248 which is fed into the three lines identified as A, B and Cphases and as shown in FIG. 1 each further amplified and finally appearsas a full threephase 400 cycle output.

What is claimed is:

1. A system for generating three-phase alternating current powercomprising, a source of direct current power, a high frequencyoscillator connected to said source of direct current power and havingan output circuit, binary frequency dividing means connected to theoutput circuit of the oscillator and dividing the high frequency of thealternating current from the oscillator in even multiples to a lowervalue, a three halves division section connected to the output of thebinary frequency dividing means to provide further frequency division, athree-phase power line and gating means connected to the three-phaseline, to the output of the binary frequency dividing means, -and to eachportion of the three halves division section to so gate the ow ofcurrent to the three-phase line as to produce a properly spacedthree-phase power output.

2. A system for generating three-phase alternating current powercomprising a source of direct current power, a high frequency oscillatorconnected to the source of direct current power and providing a highfrequency alternating current output, means for dividing the frequencyin even multiples connected to the high frequency oscillator to reducethe frequency of the output thereof, means for dividing the frequency inodd multiples connected to the output of the first-named means forfurther dividing the frequency, a three-phase output line and aplurality of gating means connected to the three-phase output line andto each portion of the outputs of the both of the means for dividing theIfrequency to provide a three-phase output.

3. In a system for generating three-phase alternating current powercomprising a source of direct current power, a high lfrequencyoscillator connected to said source of direct current power andproviding a high frequency alternating current output, frequencydividing means connected to the oscillator to provide both even multipledivision and odd multiple division frequencies, a threephase power lineand a plurality of gating circuits connected to the three-phase powerline and to the output of the even and to each portion of the oddmultiple division means to produce three-phase power on the three-phaselines.

4. In a system for generating three-phase alternating current powercomprising a source of direct current power, a high frequency oscillatorconnected to said source of direct current power and providing a highfrequency alternating current output, binary frequency dividing meansconnected to the oscillator output to reduce the frequency of thealternating current in even steps to a relatively low frequency, ternaryfrequency dividing means connected to the output of the binary frequencydividing means to provide a plurality of dephased signals having anoutput frequency of one-third of the output frequency of the binaryfrequency dividing means, a three-phase power line, a plurality ofgating circuits connected to the three-phase power line and to theoutput of the binary frequency dividing means and to each portion of theternary frequency dividing means to so gate the signals from thesepoints as to produce three-phase power on the three-phase line.

5. In a system for generating three-phase alternating current powercomprising a source of direct current power, a high frequency oscillatorconnected to said source of direct current power and providing a highfrequency alternating current output, binary frequency dividing meansconnected to the oscillator output to reduce the frequency of thealternating current in even steps to a relatively low frequency, ternaryfrequency dividing means connected to the output of the binary frequencydividing means to provide a plurality of dephased signals having anoutput frequency of one-third of the output frequency of the binaryfrequency dividing means, a three-phase power line, a plurality ofgating circuits connected to the threephase power line and to the outputof the binary frequency dividing means and to each portion of theternary frequency dividing means to so gate the signals from thesepoints as to produce a three-phase power on the threephase line,amplifier means connected to each line of the three-phase power line toindependently amplify the voltage in each phase, filter means connectedto each amplifier means to convert the square wave output of theamplifier means into sine wave form and three-phase output connectionsto combine the output of all filters.

6. In a system for generating three-phase alternating current powercomprising a source of direct current power, a high frequency oscillatorconnected to said source of direct current power and providing a highfrequency alternating current output, binary frequency dividing meansconnected to the oscillator output to reduce the frequency of thealternating current in even steps to a relatively low frequency, ternaryfrequency dividing means connected to the output of the binary'frequencydividing means to provide a plurality of dephased signals having anoutput frequency of one-third of the output frequency of the binaryfrequency dividing means, a three-phase power line, a plurality ofgating circuits connected to the three-phase power line and to theoutput of the binary frequency dividing means and to each portion of theternary frequency dividing means to so gate the signals from thesepoints as to produce three-phase power on the threephase line, amplifiermeans connected to each line of the three-phase power line toindependently amplify the voltage in each phase, filter means connectedto each amplier means to convert the square wave output of the amplitierinto sine wave form, stabilizing feedback means Ifrom the filter outputto each amplifier means to regulate each phase independently, andthree-phase output connections to combine the outputs of all filtermeans.

7. In a system for generating three-phase alternating currentpower'comprising a source of direct current power, a high frequencyoscillator connected to said source of direct current power andproviding a high frequency alternating current output, binary frequencydivider means connected to the output of the high frequency oscillatorto reduce the frequency of the alternating current in even steps to 1200cycles, a pair of binary circuits commonly connected to the output ofthe binary frequency divider means and simultaneously provided with T9,ini signals therefrom to form a ternary divider section, said pair ofbinary circuits being cross connected so that between the 1200 cyclesignals-supplied by the binary frequency divider means and the crossconnection, each of the pair of binary circuits operates at a frequencyof 400 cycles with an unbalanced wave, three separate conductive lines,and a plurality of gating circuits connected to the 1200 cycle outputand each binary circuit with 400 cycle output and to the three lines, toso time conduction periods as to produce on those lines properly phasedthreephase power.

References Cited by the Examiner UNITED STATES PATENTS OTHER REFERENCESStatic Inverter Delivers Regulated Three-Phase lower,

by M. Lilienstein; published by `Electronics (July 8, 1960),

vol. 33, No. 28; pages 55-59.

LLOYD MCCOLLUM, Primary Examiner. SAMUEL BERNSTEIN, Examiner.

1. A SYSTEM FOR GENERATING THREE-PHASE ALTERNATING CURRENT POWERCOMPRISING, A SOURCE OF DIRECT CURRENT POWER, A HIGH FREQUENCYOSCILLATOR CONNECTED TO SAID SOURCE OF DIRECT CURRENT POWER AND HAVINGAN OUTPUT CIRCUIT, BINARY FREQUENCY DIVIDING MEANS CONNECTEDTO THEOUTPUT CIRCUIT OF THE OSCILLATOR AND DIVIDING THE HIGH FREQUENCY OF THEALTERNATING CURRENT FROM THE OSCILLATOR IN EVEN MULTIPLES TO A LOWERVALUE, A THREE HALVES DIVISION SECTION CONNECTED TO THE OUTPUT OF THEBINARY FREQUENCY DIVIDING MEANS TO PROVIDE FURTHER FREQUENCY DIVISION, ATHREE-PHASE POWER LINE AND GATING MEANS CONNECTED TO THE THREE-PHASELINE, TO THE OUTPUT OF THE BINARY FREQUENCY DIVIDING MEANS, AND